1. Field of the Invention
This invention relates to a general semiconductor memory device, and particularly to a semiconductor memory device that operates in synchronization with a clock signal.
In recent years, as CPUs have become faster, the demand has arisen for semiconductor memory devices such as the DRAM (dynamic random access memory) wherein data signals are input and output at higher signal frequencies, making them capable of sustaining faster data transfer rates.
Examples of semiconductor memory devices responsive to this demand are the SDRAM (synchronous dynamic random access memory) and FCRAM (fast cycle random access memory) which achieve high-speed operations by operating in synchronization with an externally supplied clock signal.
2. Description of the Related Art
Conventional semiconductor memory devices are now described. These descriptions relate to the operations of FCRAMs and DDR-SDRAMs (double data rate synchronous random access memories) which achieve higher speeds by performing data I/O in synchronization with the rising and falling edges of the clock signal.
In FIG. 1 is diagrammed one example configuration for the memory-cell peripheral circuitry of a DDR-SDRAM and an FCRAM. The circuit diagrammed in FIG. 1 comprises a capacitor 201, NMOS transistors 202 to 212, 223, and 224, and PMOS transistors 213, 221, and 222. The PMOS transistors 221 and 222 and the NMOS transistors 223 and 224 configure a sense amp 220. In the capacitor 201, which is a memory cell, 1 bit of data is stored.
FIG. 2 is a timing chart representing a data read operation in a DDR-SDRAM having the memory-cell peripheral circuitry diagrammed in FIG. 1. Data read timing control is now described with reference to FIG. 1 and FIG. 2.
When data are being read out, a sequence of commands is input to the SDRAM, namely a precharge command PRE for precharging the bit lines BL and /BL to a prescribed voltage, a /RAS command (corresponding to the active command ACTV in FIG. 2) for row access, and a /CAS command (corresponding to the read command READ in FIG. 2) for column access. The /RAS command selects one row-system memory cell block from the core circuitry in the SDRAM, that is, a specific word line. The /CAS command selects a specific column from the selected word line, that is, a sense amp 220. The core circuitry is such that the memory cells 201 are deployed in an array structure as respecting the row and column directions, with a sense amp 220 provided for each column. Accordingly, memory cell data corresponding to the selected word line are fetched to the sense amps 220.
When an active command ACTV that is a control signal corresponding to the /RAS signal is input, the signal RASZ, which is an internal RAS signal, is generated (i.e. goes high). The signal RASZ is a signal for activating the memory core.
The signal RASZ, moreover, is a signal that causes the level of the word lines to rise, as the memory core is activated, and then activates the sense amps. For that reason, when the active command ACTV is input, in the memory core, the levels of the word lines rise in response to the signal RASZ, and the sense amp is activated. In FIG. 1 a shared sense amp is represented. When an address is input to select a word line SW, from the precharge state wherein the bit line transfer signals BLT0 and BLT1 are high, the one bit line transfer signal BLT0 will go low, and the bit lines BL and /BL in the block on the opposite side will be cut off from the sense amp 220. Meanwhile, the other bit line transfer signal BLT1 will stay high, the transistors 203 and 204 will continue to conduct, and the bit lines BL and /BL on the right side will remain connected to the sense amp. At the same time, the precharge signal PR becomes low, and the reset states of the bit lines BL and /BL are released. When in this status the sub-word line SW is selected, the NMOS transistor 202 functioning as a cell gate conducts, and data in the capacitor 201 are read on the bit line BL (corresponding to BL-0, 1 in FIG. 2).
Next, sense amp drive signals SA1 and SA2 (corresponding to SA in FIG. 2) for driving the sense amps 220 become active (going low and high, respectively), and both the NMOS transistor 212 and PMOS transistor 213 conduct. In this state, the data on the bit lines BL and /BL are read into the sense amps 220 via the NMOS transistors 203 and 204. The sense amps 220 thus drives the bit lines BL, /BL so that the data on the bit lines BL and /BL are amplified. Thereupon, data in all memory cells corresponding to selected word line are fetched to the sense amps throughout the whole SDRAM.
Next, when a read command READ that is a control signal corresponding to the /CAS command is input, the column line selection signal CL becomes high with suitable timing in the SDRAM, and a specific column is selected. Thereupon, the NMOS transistors 210 and 211 that are the selected column gates conduct, and the amplified data on the bit lines BL and /BL are read on global data busses GDB and /GDB (corresponding to GDB-0, 1 in FIG. 2). Thereupon, the parallel data read on data busses DB and /DB (not shown in FIG. 1) (corresponding to DB-0, 1 in FIG. 2) via read buffers are converted to serial data and output as data DQ.
After that, when the precharge command PRE is input, the precharge signal PR goes high, the NMOS transistors 207, 208, and 209 conduct, and the bit lines BL and /BL are precharged to a prescribed voltage VPR. Thus, with a conventional SDRAM, the bit lines BL and /BL can be reset in preparation for the next control signal (data write or data read).
With a conventional SDRAM, therefore, the cycle from the input of the first control signal (data read) until it becomes possible to input the next control signal (data write or data read) requires 8 clocks, as indicated in the data read operation diagrammed in FIG. 2.
FIG. 3 is a timing chart representing a data write operation in a DDR-SDRAM having the memory-cell peripheral circuitry diagrammed in FIG. 1, as described earlier. The timing control for this data write operation is now described with reference to FIG. 1 and FIG. 3.
When the active command ACTV is input, as in the data read operation described above, a signal RASZ (high) that is an internal RAS signal is generated, and, internally, the memory core is activated, the levels of the word lines rise, and the sense amps are activated. When the memory core is activated, the NMOS transistor 202 conducts, and the data in the capacitor 201 are read on the bit line BL (corresponding to BL-0, 1 in FIG. 3). The operation of the peripheral circuitry diagrammed in FIG. 1 was described earlier and so is not repeated further here.
Next, the sense amp drive signals SA1 and SA2 (corresponding to SA in FIG. 3) for driving the sense amps 220 become active (going low and high, respectively), and both the NMOS transistor 212 and the PMOS transistor 213 conduct. In this state, the data on the bit lines BL and /BL are provided to the sense amps 220 via the NMOS transistors 203 and 204. By driving the sense amps 220, the data on the bit lines BL and /BL are amplified.
Next, when a write command WRITE is input, the serial data simultaneously input from the outside as the data signal DQ are converted to parallel data and output on data busses DB and /DB (corresponding to DB-0, 1 in FIG. 3). Thereupon, the parallel data output on the global data busses GDB and /GDB (corresponding to GDB-0, 1 in FIG. 3) via write buffers are written to the sense amps 220 with the timing wherewith the column line selection signal CL represented in FIG. 1 goes high, and those data are furthermore stored in the capacitor 201 via the bit line BL.
After that, when the precharge command PRE is input, the precharge signal PR goes high with suitable timing, the NMOS transistors 207, 208, and 209 conduct, and the bit lines BL and /BL are precharged to a prescribed potential VPR. Thus, in a conventional SDRAM, the bit lines BL and /BL can be reset in preparation for the next control signal (data write or data read).
Accordingly, with a conventional SDRAM, the cycle from the input of the first control signal (data write) until it becomes possible to input the next control signal (data write or data read) requires 9 clocks, as indicated in the data read operation diagrammed in FIG. 3.
With a conventional SDRAM which performs such operations (data read and data write) as described in the foregoing, when successively reading out data at the same row address (same word line), data at different column addresses can be read out sequentially by sequentially selecting different columns. More specifically, because a sense amp 220 is provided for each of a plurality of columns, these sense amps 220 accommodate data having the same row address but different column addresses. That being so, if different columns are sequentially selected and data already accommodated by the sense amps 220 are read out, data read operations can be performed successively. Similarly, when data are being written via sense amps while the same word line is selected, if different columns are sequentially selected for writing, data write operations can be performed successively.
With conventional SDRAMs, however, when data are to be successively read out from different row addresses (different word lines), or when data are to be successively written to different row addresses (that is, when random access is performed), it is necessary to newly read the data in the memory cells selected by different word lines onto the bit lines BL and /BL. And, in order to read these new data onto the bit lines BL and /BL, it is necessary first to precharge the bit lines BL and /BL. Accordingly, intervals of 8 clocks and 9 clocks, respectively, are produced from the input of the first control signal until it becomes possible to input the next control signal, as is evident from FIG. 2 and FIG. 3. This production of such large time intervals constitutes an obstacle to the implementation of high-speed data read operations and high-speed data write operations.
This state of affairs has led to the development of the FCRAM as a semiconductor memory device wherewith to realize higher speeds in the random access operations described in the foregoing. The differences between the FCRAM and the SDRAM, and the control of data read timing in the FCRAM, will now be described. The configuration of the memory-cell peripheral circuitry in the FCRAM is the same as the circuit configuration diagrammed in FIG. 1.
A first difference with the SDRAM is that, in the FCRAM, data are read out from the sense amps 220 in parallel by selecting a plurality of columns at one time. Therefore, it is sufficient to drive the sense amps 220 only for a fixed time interval, wherefore the sense amp driving time can be made constant irrespective of the burst length BL (so that, for example, the sense amp driving time is the same with both BL=1 and BL=4), so that smooth row-system pipeline action can be effected.
A second difference is that, in the FCRAM, reset operations are executed automatically by an internal precharge signal (corresponding to PRE in the SDRAM). More specifically, using the fact that sense amp operations are performed in the same period, precharging is executed with optimal timing immediately after data are read from the sense amps 220. Thus data read operations can be executed in high-speed cycles near the operating limits of the sense amps 220.
A third difference is that, with the FCRAM, in the random access read cycle, when the burst length BL=4, for example, the 4 bits of parallel data read out together from the sense amps are converted to serial data, whereupon successive, uninterrupted data read out operations are realized.
FIG. 4 shows a timing chart representing the data read operation of an FCRAM having the memory-cell peripheral circuitry diagrammed in FIG. 1 and described earlier. The data read timing control is described with reference to FIG. 1 and 4, assuming a data burst length BL=4.
When an active command ACTV (ACTVREAD in FIG. 4) is input, the FCRAM generates a signal RASZ to activate the memory core selected internally. In response thereto, in the core, word line selection signals MW and SW, a bit line transfer signal BLT, and sense amp drive signals SAl and SA2 (corresponding to SA in FIG. 4) are generated with suitable timing. This causes data in the memory cells 201 to appear on the bit line BL (corresponding to BL, /BL in FIG. 4), to be fetched into the sense amps 220, and then to be amplified in the sense amps 220. Furthermore, in the FCRAM, an internal precharge signal PRE is automatically generated by the low level of the signal RASZ, after a prescribed time has elapsed since the receipt of the signal RASZ.
In response to the input of a read command READ (ACTVREAD in FIG. 4), moreover, the column line selection signal CL selected by the column address goes high, and data in the sense amps 220 are read out on the global data busses GDB and /GDB (corresponding to GDB in FIG. 4). The data so read are 4-bit data. These data are output to data busses DB and /DB (corresponding to DB in FIG. 4) via data read buffers, converted to serial data, and output to the outside as read data DQ (corresponding to DQ in FIG. 4).
The precharge signal PRE generated internally resets the bit line transfer signal BLT and the word line selection signals MW and SW, in an operation like that in the SDRAM when the precharge signal PRE is input from the outside, and also precharges the bit lines BL and /BL to a prescribed potential. This precharge operation resulting from the precharge signal PRE is timed to occur immediately after data are read out from the sense amps 220 by the column line selection signal CL. In the FCRAM, moreover, the active command ACTV and read command READ are input as an active read command ACTVREAD.
When the data read operation described above is executed repeatedly, the random access read cycle is shorter in the FCRAM than in the SDRAM, and, as diagrammed in FIG. 4, the cycle from the input of the first control signal ACTV until it becomes possible to input the next control signal ACTV can be significantly reduced. Thus data read operations can be done at higher speeds with the FCRAM than with the SDRAM.
With the conventional FCRAM, as described in the foregoing, all data in memory cells selected by word lines can be fetched to corresponding sense amps by generating a memory core activation signal RASZ based on the command signal input timing, and thus high-speed data read operations are realized.
However, when the memory core activation signal RASZ is generated based on the command signal input timing, the time from when a command signal is fetched until when the memory core activation signal RASZ becomes active is fixed. As a consequence, the following problems occur during data write operations.
Given a burst length of BL=4, for example, even though it is possible to write data accurately when data write operations are executed in synchronization with a clock signal of a certain frequency, there are cases where accurate write operations cannot be done with a clock signal having a lower frequency than that certain frequency. A problem arises, in other words, in that the memory core activation signal RASZ automatically becomes active after a prescribed time has elapsed, even though the data fetching frequency is low, whereupon the write operation to the sense amps begins before all the data in the burst length can be fetched, so that the remaining data are not written. Depending on the frequency of the synchronizing clock signal, moreover, this problem can arise in data write operations at all burst lengths other than BL=1.
Another problem arises in that one of the characteristics of the FCRAM, namely that the operation cycle (or command cycle) is short even in cases of random access, may be lost, depending on the burst length during write operations. Cases are conceivable, for example, where the operating frequency becomes low despite the fact that the burst length is long, in which cases it will become very difficult to effectively fetch all write data in a short operation cycle.
An object of the present invention is to provide a semiconductor memory device for effecting high-speed data write processing and data read processing, capable of accurately writing all data of settable burst lengths.
Another object of the present invention is to provide a memory circuit wherewith read operations and write command cycles can be shortened even if by limiting the freedom allowed to the burst length.
Another object of the present invention is to provide a memory device wherein the command cycle is shortened during write operations performed by random access.
Another object of the present invention is to provide a memory device wherein row addresses and column addresses are input simultaneously, and the write command cycle is shortened.
Another object of the present invention is to provide a memory device capable of effectively operating with different burst lengths, wherein the write command cycle is shortened.
Thereupon, in order to resolve the problems described in the foregoing, a first aspect of the present invention is a semiconductor memory device operating in synchronization with a clock signal, having a burst length setting circuit for setting burst length, and a control signal generator circuit for generating a control signal for activating a memory core, in response to fetched command signal; wherein the control signal generator circuit outputs the control signal in response to the timing wherewith the command signals are fetched, during data read and data write operations, with substantially the same timing irrespective of the burst length.
According to the invention described above, during read and write operations, memory core activation signals are generated, after command signal input, with equal timing unrelated to the burst length. Accordingly, a memory circuit can be provided which operates with the same command cycle during successive read operations, successive write operations, and when read and write operations are being performed alternately.
The semiconductor memory device of the present invention defines a maximum value for the burst length that can be set by the burst length setting circuit, in accordance with the frequency of the clock signal for fetching serial write data. That is, it is guaranteed that all serial data will be fetched into the device from the timing wherewith a command signal is fetched until a control signal is generated a certain interval of time thereafter and the memory core is activated. In order thereto, a maximum value of the burst length settable by the burst length setting circuit is defined that is compatible with the clock frequency. That being so, the semiconductor memory device of the present invention can accurately write all data of the set burst length, even if a memory core activation signal is generated, with equal timing that is unrelated to the burst length.
Furthermore, in a preferred embodiment of the first aspect of the present invention, the interval from the timing wherewith a write command signal is fetched until the timing wherewith the next read command signal is fetched is made the same as the interval from the timing wherewith a read command signal is fetched until the timing wherewith the next read command signal is fetched. Here the command cycle Trc, which is the interval at which command signals are input, is always constant at the minimum value. That is, the input intervals from read command to read command, from write command to write command, from read command to write command, and from write command to read command are always constant. As a consequence, a memory device can be provided wherein the command cycle is constant and short.
In another preferred embodiment of the first aspect of the present invention, when the command signal noted in the foregoing is a read command signal, the time from the timing wherewith that read command signal is fetched until data are read out is longer than the interval noted in the foregoing. Here, the memory core and a command decoder constitute a pipeline configuration, for example, in order to effect high-speed data read and data write operations.
Next, a second aspect of the present invention is a semiconductor memory device operating in synchronization with a clock signal, having a control signal generator circuit for generating a control signal for activating a memory core, based on fetched command signals; wherein the control signal generator circuit, when the command signal is read command signal, outputs the control signal in response to the timing wherewith the read command signal is fetched, and when the command signal is write command signal, outputs the control signal in response to the timing wherewith the n""th write datum in a sequence of write data in the burst length is fetched.
According to the invention described above, all data in a settable burst length can be accurately written, whereupon high-speed data write processing and data read processing is realized. The variable n noted here is an integer the maximum value whereof is the burst length. This integer may be smaller than the burst length.
In the semiconductor memory device in the second aspect of the present invention, described in the foregoing, all sererg danside the device, and the control signal generator circuit is controlled so that a control signal is generated after a certain time has elapsed since that condition was attained. Accordingly, the semiconductor memory device of the present invention can write all data in a set burst length irrespective of the clock frequency. In other words, high-speed data write processing and data read processing are realized without placing limitations on either the settable burst length or the clock frequency wherewith write data are fetched.
A preferred embodiment of the second aspect of the present invention, described above, has a burst length setting circuit (corresponding to a mode register 4 in a second and third embodiment described below) for setting the burst length for read data and write data, wherein the contator circuit outputs the control signal based on the burst length set. An example of a specific configuration for setting a discretionary burst length is here indicated.
In a preferred embodiment of the second aspect of the present invention, described above, when all the bits of the write data in a set burst length can be fetched within a specific time, the control signal generator circuit outputs the control signal in response to the timing wherewith the first bit thereof is fetched. One example of a method for generating control signal in a control signal generator circuit is here defined.
A preferred embodiment of the second aspect of the present invention, described in the foregoing, has a burst counter (corresponding to a burst counter 51 in the second and third embodiments described below) for counting the number of bits of write data fetched, and the control signal generator circuit comprised therein, when all bits in the write data of a set burst length can not be fetched within a specific time, outputs the control signal in response to the timing wherewith the n""th write datum of the write data in the burst length is fetched. Another example of a method for generating control signal in a control signal generator circuit is here defined.
In a preferred embodiment of the second aspect of the present invention, described above, the interval from the timing wherewith the write command signal is fetched to the timing wherewith the next read command signal is fetched is made the same as the interval from the timing wherewith a read command signal is fetched until the timing wherewith the next read command signal is fetched. Here, the command cycle Trc, which is the interval at which command signals are input, is defined to be a minimum value that is constant.
In a preferred embodiment of the second aspect of the present invention, described above, when the command signal is a read command signal, the time from the timing wherewith the read command signal is fetched until the timing wherewith the data are read is made longer than the interval noted in the foregoing (command cycle). It is here indicated that pipeline processing is performed in order to realize high-speed data read and data write operations.
A third aspect of the present invention is a semiconductor memory device operating in synchronization with a clock signal, having a control signal generator circuit for generating a control signal for activating a memory core, in response to fetched command signal, and a burst length setting circuit for setting burst length; wherein the control signal generator circuit has a first circuit for outputting the control signal during data read and data write operations in response to the timing wherewith the command signal is fetched, with timing unrelated to the burst length, and a second circuit for outputting the control signal during data read operation in response to the timing wherewith the command signal is fetched, and for outputting the control signal during data write operation in response to the timing wherewith the n""th write datum in a sequence of write data is fetched; and wherein the first circuit and the second circuit are switched according to the frequency of the clock signal and the set burst length.
According to the third aspect described above, all the data in a settable burst length can be accurately written, and a third specific configuration example is defined for realizing high-speed data write processing and data read processing. The variable n noted here is an integer the maximum value whereof is the burst length. This integer may be smaller than the burst length.
In the semiconductor memory device of the present invention, when operating with the first circuit, for example, a maximum value for the settable burst length is defined, for each clock frequency, in the burst length setting circuit, so that all serial data are fetched into the device by the time that a control signal is generated after a specific time has elapsed since the timing wherewith the command signal was fetched and the data in the memory cells have been read into the sense amps. Accordingly, all data in the set burst length can be accurately written. When operating with the second circuit, on the other hand, the control signal generator circuit is controlled so that all serial data are fetched into the device, and a control signal is generated after a certain time has elapsed since that state. Accordingly, in this case also, all the data in the set burst length can be accurately written in, irrespective of the frequency of the clock signal.
A fourth aspect of the present invention is a memory circuit having a prescribed burst length and operating in synchronization with a clock signal, having a memory core having a plurality of memory cells and a sense amp group connected to those memory cells via bit lines, and a control signal generator circuit for generating a control signal for activating the memory core in response to fetched command signal; wherein the control signal generator circuit, during data read and data write operations, outputs the control signal in response to the timing wherewith the command signal is fetched, after a fixed delay time, irrespective of the burst length; and the command cycle is a constant number of clocks when the data read and data write operations are performed in random fashion.
According to the fourth aspect described above, by limiting the burst length to some degree, the command cycle can be made as short as possible even when read and write operations are performed in random fashion, thus facilitating high-speed random access.
A fifth aspect of the present invention is a memory circuit having a prescribed burst length and operating in synchronization with a clock signal, comprising: a first stage for decoding command signal; a second stage, including a memory core having a plurality of memory cells and a sense amp group connected to those memory cells via bit lines, for performing pipeline operation with the first stage; and a control signal generator circuit for generating control signal for activating the memory core, based on fetched command signal; wherein the control signal generator circuit, when the command signal is a read command signal, outputs the control signal after a certain delay time following the fetching of that read command signal, and, when the command signal is a write command signal, outputs the control signals after a delay time determined according to the burst length, following the fetching of that write command signal.
A sixth aspect of the present invention is a memory circuit for writing prescribed numbers of bits of write data, determined according to the burst length, in response to write command, comprising: a first stage for inputting, and then holding, row addresses and column addresses simultaneously with the write command; a second stage having a memory core connected to the first stage via a pipeline switch, wherein the row addresses and column addresses are decoded, and word line and sense amps are activated; a third stage for inputting the write data serially and sending the write data to the memory core in parallel; and a serial data detection circuit for generating write-pipeline control signal for making the pipeline switch conduct, after the prescribed number of bits of write data has been inputted.
According to the sixth aspect of the present invention, in an FCRAM exhibiting a pipeline structure, the memory core in the second stage can be activated after safely fetching the write data in the burst length. When writing successively or reading successively, moreover, the command cycle can made short irrespective of the burst length.